Expected Phase Code Jitter?

I seem to be getting higher than expected jitter on my phase code routine.

If I create and run an empty user phase routine, I am getting about +/-8% jitter when the phase interrupt is set to 18kHz (i.e. the measured time between phase code executions varies between 49-60 us, and the nominal is 55 us).

I am using fclock() inside the phase code and writing the calculated time to a Pvar to measure the time between phase code executions.

That is not actually bad at all. Remember the ADCs are latched on the falling phase clock edge and the outputs transmitted on the next falling edge. So as you are not using 50% of the duty cycle you will be fine.