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Can multiple axis have logical hardware position compare output
#1
Dear sir,
Here is an application that we want to use Clipper's hardware position compare.
Can we set it up to have logical output? Such as A & B axis have all passed their set point, then came one output.
This should also be a hardware position compare, if it use PLC to compare, it will be too slow.
Is it possible?
I can’t find it in the manual.
Thank you!

Ning Liu
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#2
As a general answer:
In DSPGate1, designed for use with Turbo or Non-Turbo PMAC2, Each channel has its own position compare functionality. The position compare can word based upon its own encoder input (I7mn1=0) or based upon 1st channel's encoder input (I7mn1=1). In the first case (I7mn1=0) each EQU output would be independent. In the second case where both compare functions use the 1st channel's encoder input, the output of the 1st channel would be the logical AND of the both compares, while the higher channel's output would be only that channels position compare result.

In case of your application, one of the following would be the solution:

(1)If both of the channels use the same encoder:
Then you can use this built-in logical AND functionality and use 1st channel's EQU output as a logical AND of the compare signals.

(2)If your axis are independent and you want to perform a logical operation on them, it has to be done with an external electrical circuit which can be achieved in 2 ways:
(2-A) An external logic gate which takes the EQU outputs from JMACH2 connector and does the operation off-board.
(2-B) Use the option-11 programmable FPGA part with a custom code, which performs the logical operation in the FPGA U90 on-board and outputs on pins 19 through 23 of JHW.
Clipper’s Option 11 consists of a programmable lattice chip which can be programmed based upon customer’s requirements. Different
programs can be loaded in this chip based upon customers requirements and each code will be designated an alpha-numeric suffix after options number if the code is developed by Delta Tau and can be ordered at a later time with the same suffix.
Please refer to Clipper's hardware reference manual for an example implementation of logic code on this FPGA. Your custom code would be different from Option-11A code, but it can be developed if ordered.
Sina Sattari
Hardware Engineering Manager
Delta Tau Data Systems, Inc.
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#3
Dear Sina,
Thank you very much!
But I have seen this in the "Turbo Pmac User Manual"(September 12, 2008), in page 346:
"1.) This control bit has been assigned an I-variable – I7mn1 for Servo IC m Channel n. Note that when multiple compare circuits have been assigned to Channel 1 of a Servo IC, the compare output for the first channel is the logical OR of all of the compare logical outputs assigned to Channel 1."
Does this manual got wrong? I know you are the Chief Engineer. :)
Thank you!

Ning Liu
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#4
Ning Liu,

I'm afraid the manual is wrong and logical AND is correct. We have made a few corrections to the manual and this one is one of them. We'll update the manual on the website soon with these changes.

Regards,
Sina Sattari
Hardware Engineering Manager
Delta Tau Data Systems, Inc.
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#5
Thank you very much !
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#6
Dear Sina,
I have seen that the SRM had already been updated, “logical OR” had been changed to “logical AND” in “I7mn1”.
But there is a technical note “Position Compare Examples” also used this feature to achieve “Even Intervals Limited to Specific Region”.
(http://www.deltatau.com/Common/technotes...amples.pdf page 4)
So, this example is based on theory, not on experiment? This note should also be updated?
Thank you very much!
Best Regards,
Ning Liu
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#7
It seemed nobody like to answer this question :), and I am a trouble maker.
The fact is I do not have a platform with me now, so I can't test it myself. But we will have a big project, and I want to use this feature in that project.
If I am sure it is logical AND or logical OR,then I can use it directly, if there is something wrong with my program, I do not have to doubt this function.
Thank you !
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#8
Inn365,

Thanks for pinging on this question. I ran a quick test and it shows that enabling the I7mn1 in Turbo PMAC or Gate1[i].Chan[j].Equ1Ena for Power PMAC results in logical OR of both EQU signals on 1st channel's EQU output.

Here is my test setup parameters:
Code:
Acc51E[6].chan[0].outputmode=3
Acc51E[6].chan[1].outputmode=3
Acc51E[6].Chan[0].EncCtrl=8
Acc51E[6].Chan[1].EncCtrl=8

Acc51E[6].Chan[1].Equ1Ena=1


Acc51E[6].Chan[0].Pfm = 0

Acc51E[6].Chan[1].CompAdd = 1000
Acc51E[6].Chan[1].CompA = Acc51E[6].Chan[0].PhaseCapt + 250
Acc51E[6].Chan[1].CompB = Acc51E[6].Chan[0].PhaseCapt - 250
Acc51E[6].Chan[1].EquWrite=3

Acc51E[6].Chan[0].CompAdd = 100
Acc51E[6].Chan[0].CompA = Acc51E[6].Chan[0].PhaseCapt + 25
Acc51E[6].Chan[0].CompB = Acc51E[6].Chan[0].PhaseCapt - 25
Acc51E[6].Chan[0].EquWrite=1

Acc51E[6].Chan[0].Pfm = 65536

And here is a screenshot from my oscilloscope:

   
Sina Sattari
Hardware Engineering Manager
Delta Tau Data Systems, Inc.
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#9
Dear Sina,
Thank you for your patience. Then the SRM seems have to be updated again :)
Love you!

Best Regards,
Ning Liu
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