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Data Packing - Printable Version

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+--- Thread: Data Packing (/showthread.php?tid=2927)



Data Packing - gmschoon - 07-11-2019

We are trying to setup data packing for an application and have the following configurations, using firmware version 2.4.0.180.

Setup 1 for data packing (step 1 of motor test/commission window shows Adc0 responding as expected, but Adc1 is fixed at -16711936 which suggests the data is being packed but not interpreted correctly):
PackOutData = 1
PackInData = 2
PhaseCtrl = 1

Setup 2 for data packing (same result as above):
PackOutData = 1
PackInData = 3
PhaseCtrl = 1

Setup for unpacked data (works as expected):
PackOutData = 0
PackInData = 0
PhaseCtrl = 4

We may be able to proceed using unpacked data, however if someone can point out any config settings that may have been missed it would be much appreciated.

Thanks


RE: Data Packing - curtwilson - 07-11-2019

If the current feedback registers are "packed", only the high 16 bits of each 32-bit source register are packed into the single 32-bit resulting register.

This is enough to get the current feedback data itself back to the CPU, but many direct PWM drives, including the Power Brick drives, use multiple lower bits as important status information. Trying to pack the data in these drives typically will not work due to the loss of these status bits.


RE: Data Packing - Eric Hotchkiss - 07-15-2019

PackInData = 3 will unpack the AdcEnc[k] registers, which may matter if you have a sinusoidal encoder or resolver.